A precedence detector is a circuit for determining which of two signals occurs first. Various previous techniques have been used. For instance, using one signal to clock a D-type flip-flop, with the second signal applied to the "D" input. These have had the disadvantage that they provided no convenient method to compensate for differing delays in the signal transmission paths, and could contain an inherent off-set in the detector itself (related, for example, to the set up and hold times of a "D"-type flip-flop).
In making the determination of which signal occurred first, it is important to consider the physical location of the points at which the signals are to be compared. This includes the path that is necessary to transmit the signals to the precedence detector circuit. If the two transmission paths have unequal delays, whether it be because of different wire lengths or different propagation speeds of devices intermediate to the signal source and the precedence detector circuit, then the signals arriving at the inputs to the precedence detector circuit will have a different time relationship than those at the measurement points which are of interest.
In accordance with the preferred embodiment of the present invention, these transmission path delay differences can be cancelled through the use of a balancing technique. To balance the precedence detector, calibration signals known to be coincident in time are applied to the source points of the signals whose relative occurrence in time is to be determined. If the two source points are located at approximately the same point, then the same signal can be applied to both inputs. The balancing operation is then performed.
In another application, balancing of the precedence detector circuit can be performed with calibrating signals at the two source points that may differ in time. In this case, future precedence measurements compare the relative timing of the measured signals to that of the calibration signals.
In accordance with the preferred embodiment of the present invention, first and second input signals are received. The first input signal is used to trigger a ramp voltage generator which provides a ramp output signal. This ramp output signal and a preselected voltage reference signal are applied to a comparator whose output signal indicates the relative values of the ramp signal voltage and the preselected voltage reference signal. The second input signal is delayed by a fixed time period and thereafter causes the providing of a sampling signal which is used to sample the comparator output signal. The value of the comparator output signal at the time of sampling indicates the relative occurrence of the first and second input signals.